1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method for fabricating a nonvolatile memory device.
2. Background of the Related Art
Effective sizes of memories, which determine packing densities of nonvolatile memory devices such as flash electrically erasable programmable read only memories (flash EEPROMs) and EEPROMs, depend on sizes of cells and array structure of cells. In an aspect of memory cells, a smaller or minimum cell structure is a simple stacked structure.
A conventional nonvolatile memory device having a simple stacked structure is shown in FIG. 1. A floating gate 13 is formed on a tunneling oxide layer 12 formed on a p-type semiconductor substrate 11. Over the floating gate 13, there is formed a control gate 15. A dielectric layer 14 is formed between the control gate 15 and the floating gate 13. N-type impurity regions 16 are formed beneath the surface of the semiconductor substrate 11 at both sides of the floating gate 13.
As shown in FIG. 2, in an array of memory cells having a simple stacked nonvolatile memory device, word lines 17 are formed on a semiconductor substrate (not shown) in a first direction spaced apart from one another by a predetermined distance. Metal bitlines 18 are formed in a direction at right angles to the word lines 17 and spaced apart from one another by a predetermined distance. One common drain line 20 per two word lines 17 is formed in the same direction as the word lines 17. However, since one metal contact hole 19 is needed per two cells, an effective size of a memory cell becomes large.
To solve such a problem, FIG. 3 illustrates an array circuit diagram showing a nonvolatile memory device, and FIG. 4 is a cross-sectional view showing a structure of the nonvolatile memory device taken along line IV--IV of FIG. 3.
In the nonvolatile memory device of FIG. 3, source and drain impurity regions 29 are used as bitlines. That is to say, a plurality of pairs of n-type heavily doped impurity regions are formed in a direction spaced apart from one another by a predetermined distance. Word lines 23 are formed at right angles to the source and drain impurity regions 29 spaced apart from one another by a predetermined distance. At this time, the pairs of the impurity regions are isolated by isolating layers 28. A pair of impurity regions are used as a source and a drain as well as n.sup.+ bitlines 29.
Floating gates 24 are formed between the word lines 23 and pairs of impurity regions. At this time, the word line 23 over the floating gates 24 becomes a control gate. A dielectric layer 26 is formed between the control gate and the floating gate 24, and a gate code oxide layer 27 is formed between the floating gate 24 and the semiconductor substrate 21.
At the ends of the n.sup.+ bitlines 29 (i.e., source and drain impurity regions) there are placed a plurality of selection transistors 30 for selecting the n.sup.+ bitlines 29. Metal contact holes 31 are connected to a plurality of selection transistors 30. The metal contact holes 31 connect the selection transistors 30 with metal data lines (not shown).
As described above, in the conventional nonvolatile memory device of FIG. 3, one metal contact hole per 32 cells or more than 32 cells is needed because of smaller resistances of impurity regions even though a bitline per a cell is not formed. Thus, smaller effective cell sizes are required.
However, in the conventional nonvolatile memory devices of FIGS. 3-4, two adjacent cells along the direction of word lines are under the same bias condition. Thus, program disturb can be generated so that a non-selected cell is programmed or erased. To solve such program disturb problems, bitlines are separated from one another to separate sources and drains between adjacent cells or asymmetric channel-dividing cells having selection gates are used as memory cells.
FIG. 5 is a circuit diagram of an array of a conventional nonvolatile memory device in which sources are separated from drains. As shown in FIG. 5, since a source and a drain of each cell are separated, pairs of source lines and drain lines 32 and 33 are formed in a direction to be spaced apart from one another by a predetermined distance. The source lines 32 are connected to n-type heavily doped source impurity regions (not shown) and the drain lines 33 are connected to the n-type heavily doped drain impurity regions (not shown). Word lines 23 are formed at right angles to the source and drain lines 32 and 33.
Each of metal data lines 34 is formed at one end of the drain lines 33 and in the same direction as the drain lines 33. A plurality of selection transistors 30 are formed at ends of the source and drain lines 32 and 33. Metal contact holes 31 are connected to the selection transistors 30. The metal contact holes 31 connect the selection transistors 30 and the metal data lines 34. However, the conventional nonvolatile memory device having the source and drain of each cell separated disadvantageously increases a size of the unit cell because of the division of bitlines.
In a related art nonvolatile memory device as shown in FIG. 6, a floating gate 24 is formed on a gate oxide layer 27 formed on a p-type semiconductor substrate 21. A control gate 25 is formed over the floating gate 24. A selection gate 35 is formed on the gate oxide layer 27 and over the control gate 25. A dielectric layer 26 is formed between the selection gate 35 and the control gate 25 and the floating gate 24. The dielectric layer 26 is also formed between the control gate 25 and the floating gate 24. A pair of n-type source and drain regions 22 are formed beneath the surface of the semiconductor substrate 21. At this time, one of the source and drain regions 22 is formed to be aligned with one side of the floating gate 24 and the other of the source and drain regions 22 is formed to be spaced apart from the other side of the floating gate 24. However, the related art nonvolatile memory device in which channel-dividing cells have an asymmetrical structure disadvantageously increases a size of a unit cell because of the selection gates.